1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming gate electrodes on a vertical transistor device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, vertical transistors, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1 is a simplistic and schematic depiction of an illustrative prior art vertical transistor device 10. In general, the vertical transistor 10 comprises a generally vertically oriented channel semiconductor structure 12A that extends upward from a front surface 12S of a semiconductor substrate 12. As indicated in the right-hand portion of FIG. 1, the semiconductor structure 12A may have a variety of different configurations when viewed from above, e.g., circular, rectangular, square, etc., and it has an outer perimeter 12P. The device 10 further comprises a channel region 13, a gate-all-around (GAA) gate structure 14 that is positioned around the perimeter 12P of the semiconductor structure 12A, a bottom source/drain (S/D) region 16, a top S/D region 18, a bottom spacer 15B, and a top spacer 15T. Also depicted is an illustrative bottom contact 20 that is conductively coupled to the bottom S/D region 16 and a top contact 22 that is conductively coupled to the top S/D region 18. In the depicted example, the gate structure 14 comprises a gate insulation layer 14A and a conductive gate electrode 14B. The materials of construction for the components of the device 10 may vary depending upon the particular application. The gate structure 14 may be manufactured using well-known gate first or replacement gate manufacturing techniques.
Device designers and manufacturers are constantly in search of device designs and methods of manufacturing that improve device performance, processing efficiencies and/or product yields. The formation of vertical transistor devices can present some special challenges. For example, the gate electrode 14B may be formed by depositing a metal layer between a plurality of closely spaced transistor devices and recessing the metal layer. It may be difficult to control the initial height of the metal layer and its post-recess height due to varying pitch between transistor devices 10 in different regions of the integrated circuit device and the effects of the pitch on the deposition and etch processes.
The present disclosure is directed to methods of simultaneously forming bottom and top spacers on a vertical transistor device that may solve or at least reduce the effects of one or more of the problems identified above.